1. Field of the Invention
The present invention relates to a pulse delay circuit constituted of a plurality of delay units each of which is configured to delay a pulse signal inputted thereto by a delay time depending on the voltage level of an input voltage signal applied thereto, and an A/D converter including the pulse delay circuit.
2. Description of Related Art
There is known an A/D converter of the pulse delay type (TAD type), which is entirely constituted of digital circuits.
The A/D converter of the TAD type includes a pulse delay circuit constituted of delay units connected in series or in a ring each of which is configured to delay a pulse signal inputted thereto by a delay time depending on the voltage level of an input voltage signal applied thereto. This A/D converter outputs numerical data showing the number of the delay units which the pulse signal has passed through as A/D converted data. The A/D converter of the TAD type can be manufactured easily and at low cost by use of the CMOS digital circuit manufacturing technique, because it is constituted of digital circuits only.
Incidentally, for the A/D converter of the TAD type to operate stably, it is necessary that all the delay units constituting the pulse delay circuit have a uniform delay time, so that the pulse signal travels while being uniformly delayed in succession (see FIG. 6A). FIG. 6A is a diagram schematically showing variation of the output level of each of the delay units when the pulse signal travels in the pulse delay circuit. In this figure, “Pi” denotes a delay pulse outputted from the i-th stage delay unit when the pulse signal has passed through this i-th stage delay unit.
Meanwhile, with the progress of CMOS circuit miniaturization, the effects of manufacturing tolerance and minute dust during a transistor forming process on the performance of the formed transistors is becoming larger. If there is large transistor-to-transistor variation in driving capacity, since there occurs large unit-to-unit variation in delay time as shown in FIG. 6B, the resolution of A/D converted data (the voltage width of the input voltage signal corresponding to 1 LSB) varies to an unallowable extent.
To cope with such a problem, it is known to make the transistors constituting the pulse delay circuit which affects the resolution of A/D converted data larger in size than the transistors constituting other circuits or units of the A/D converter which do not affect the resolution of A/D converted data, in order to lessen the effects of manufacturing tolerance or minute dust on the performance of the transistors constituting the pulse delay circuit. For example, refer to Japanese Patent application Laid-open No. 2007-6369.
However, since each of the delay units constituting the pulse delay circuit is usually constituted of CMOC inverter gate circuits, switching noise is superimposed on the power supply line of the delay units, that is the signal line through which the input voltage signal is applied to each delay unit, each time the output of each CMOS inverter gate circuit inverts its state.
Accordingly, when the transistors constituting the pulse delay circuit are made large in size, the switching noise increases because electric power consumed by each delay unit increases.
As a result, since the level of the input voltage signal varies greatly due to the switching noise, there occurs variation in delay time among the delay units as shown in FIG. 6B, the pulse delay circuit cannot output the delay signals P1, P2, . . . at even time intervals while the pulse signal travels in the pulse delay circuit.